Synopsys lifts 2026 outlook as AI chip race drives design-tool demand

On Wednesday, Synopsys announced an increase in its full-year revenue and earnings guidance, a sign of the billions being spent on AI making their way down to the software that powers the chip design.

The California company, whose software is part of almost every high-end chip that is being developed, added that the increasing use of AI has forced its clients to create more complex chips on tighter schedules.

The implications are not restricted to one earnings report. Synopsys plays an important role in the AI supply chain: before chips from companies such as Nvidia or AMD or a hyperscaler’s proprietary program reach a fabrication plant, they usually go through electronic design automation software developed by Synopsys or a competitor like Cadence.

Thus, an improved outlook from Synopsys can indicate the level of expenditure by companies developing the next-generation AI infrastructure.

AI demand pushes the forecast higher

As per data published in its third quarter results, Synopsys has revised its expected revenues in the fiscal year 2026 to between $9.69 billion to $9.74 billion, thus increasing the previous range on both sides where $9.71 billion was the upper limit. Adjusted earnings estimate for the company has also gone up from earlier $14.72-$14.80 per share to $15.04-$15.10 per share.

Both the predictions are ahead of Wall Street’s expectations. According to the data provided by LSEG and quoted by Reuters, analysts had anticipated $9.68 billion in revenue and $14.76 in profit per share for the year.

Results for the third quarter were also above predictions. Revenue grew to $2.477 billion for the three months ending July 31 compared to $1.740 billion during the same time last year. The adjusted earnings of $3.91 per share surpassed analyst expectations of $3.67 per share.

According to CFO Shelagh Glaser, the company’s positive performance can be traced to AI investments. “The growth is really underpinned by the strong design environment we’re seeing, and the main thing driving it is AI,” she said in an interview with Reuters. Despite that, Synopsys stock fell by approximately 2% in after-hours trading.

What the numbers say about global AI spending

This positive guidance from Synopsys correlates well with a general trend in semiconductor industry expenditure. On August 24, Gartner predicted that worldwide semiconductor revenues will reach $1.6 trillion by 2026, a pronounced increase of 92% from $809 billion in 2025. In addition, the forecaster predicts that the share of AI data centers in the market will increase from 36.5% this year to 53% by 2030.

“The semiconductor industry is entering a fundamentally new phase of growth,” said Gartner director analyst Ben Lee, indicating considerable investment in AI infrastructure.

The same pattern is now being picked up in design software. The ESD Alliance, a SEMI coalition, reported that revenues from electronic system design hit $5.75 billion in the first quarter of 2026, which is an increase of 12.7%, with semiconductor IP and computer-aided design contributing significantly.

Cadence also signaled this in July, as it raised its growth forecast for 2026 to 19%, in addition to a record backlog of $8.1 billion reported by the company. According to Anirudh Devgan, CEO of Cadence, “Cadence is leading the agentic AI transformation in semiconductor design,” claiming that this is a “massive TAM expansion opportunity.”

In-house chips and autonomous design workflows

Another force driving Synopsys is the growing number of companies designing their own chips. Cloud giants including Amazon and Alphabet are expanding in-house silicon programs, Reuters reported, broadening a market once dominated by a small group of merchant chipmakers. Those custom accelerators still require design tools, verification software and licensable chip components.

Synopsys’ design IP business reflected that demand, returning to year-over-year growth in the third quarter, with another increase expected this quarter.

“Customers are building more and more complex chips and in shorter time frames. And we offer the tools for them to simplify that complexity,” Glaser said.

Synopsys is also automating more of the design process itself. At the DAC conference in July, it introduced autonomous “agentic” EDA workflows developed with Microsoft and used by AMD. Early evaluations showed debug cycle times falling 25% to 40%.

CEO Sassine Ghazi summed up the pressure facing chip designers: “AI is driving unprecedented complexity” in the silicon required to power the next generation of AI systems.